View HT1130_199519.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT1130 4-bit Microcontroller
Features
* * * * * * * * * *
Operating voltage: 2.4V~3.3V 12 input lines Four output lines Five working registers Sound effect circuit 4K 8 program ROM 128 4 bits data memory RAM size 32 4 segment LCD driver RC oscillator for system clock Halt feature reduces power consumption
* * * * * * *
Internal timer overflow interrupt External interrupt One level subroutine nesting 8-bit timer with internal or external clock source 8-bit table read instruction Up to 4ms instruction cycle with 1MHz system clock at VDD=3V All instructions in 1 or 2 machine cycles
General Description
The HT1130 is a processor from Holtek s 4-bit stand alone single chip microcontroller range specifically designed for LCD product applications. The device is ideally suited for multiple LCD low power applications among which are calculators, scales and hand-held LCD products.
1
May 24, 1999
HT1130
Block Diagram
S ta c k T im e r OSCI OSCO IN T RES TEST1 TEST2 T1D T256 VLC D VDD VSS ALU PA ACC
TM C LK
C on an T im C ir c
tro l d in g u it
PC
PA0 PA1 PA2 PA3
PP ROM R0 In s tr u c tio n D ecoder R1 R2 R3 PM R4 PS
PP0 PP1 PP2 PP3
PS0 PS1 PS2 PS3
PM0 PM1 PM2 PM3
T e m p o ra ry D a ta R A M D is p la y D a ta R A M
Sound E ffe c t
BZ BZ
L C D D r iv e r
Notes: ACC: Accumulator PC: Program counter R0~R4: Working registers
SEG0
SEG1
SEG 30
2
SEG 31
PA: Output port PS,PM,PP: Input ports
COM0
COM1
COM2
COM3
May 24, 1999
HT1130
Pad Assignment
SEG 31 65 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19 SEG 18 VDD 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 19 VSS 20 OSCI OSCO T1D PA3 PA2 PA1 PA0 22 23 24 25 26 27 PP0 28 PP1 29 PP2 30 PP3 31 IN T 32 RES (0 , 0 )
BZ BZ VLCD T256 COM3 COM2 COM1 COM0 TEST1 TEST2 PM3 PM2 PM1 PM0 PS3 PS2 PS1 PS0
64
63
62
61
60
59
58
57
56
55
54
53
55 12 .
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG 17 SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 TM CLK
Chip size: 2790 3000 (mm)
2
* The IC substrate should be connected to VSS in the PCB layout artwork.
3
May 24, 1999
HT1130
Pad Coordinates
Pad No. 1 2 3* 4* 5 6 7 8 9* 10* 11 12 13 14 15 16 17 18 19* 20* 21* 22* 23 24 25 26 27 28 29 30 31* 32* 33 X -1192.10 -1192.10 -1196.70 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -1261.10 -876.70 -719.70 -542.10 -406.70 -276.30 -140.90 -10.50 124.90 284.90 427.40 570.90 713.40 856.90 999.40 1261.10 Y 1305.20 1169.80 1019.80 873.70 731.20 587.70 445.20 301.70 159.20 15.70 -126.80 -270.30 -412.80 -556.30 -698.80 -842.30 -984.80 -1128.30 -1331.40 -1331.40 -1241.00 -1241.00 -1241.00 -1241.00 -1241.00 -1241.00 -1331.40 -1331.40 -1331.40 -1331.40 -1331.40 -1331.40 -1265.80 Pad No. 34* 35* 36* 37* 38* 39* 40* 41* 42* 43* 44* 45* 46* 47* 48* 49* 50* 51* 52* 53* 54* 55* 56* 57* 58* 59* 60 61 62 63 64 65 66* X 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1261.10 1001.00 858.50 715.00 572.50 429.00 286.50 143.00 0.50 -143.00 -285.50 -429.00 -571.50 -715.00 -857.50 -990.50 Unit: mm Y -1122.30 -979.80 -836.30 -693.80 -550.30 -407.80 -264.30 -121.80 21.70 164.20 307.70 450.20 593.70 736.20 879.70 1022.20 1165.70 1311.20 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40 1331.40
* These pins must be bonded out for function testing.
4 May 24, 1999
HT1130
Pad Description
Pad No. 1, 2 3 4 22 9 10 5~8 11~14 15~18 19 20 21 23~26 Pad Name BZ, BZ VLCD T256 T1D TEST1 TEST2 COM3~COM0 PM3~PM0 PS3~PS0 VSS OSCI OSCO PA3~PA0 I/O Mask Option O I O O I I O I I I I O O Note 1 3/4 Function Sound effect outputs (+) LCD bias power supply For test mode only TEST1 and TEST2 are left open when the HT1130 is in normal operation (with an internal pull high resistor). Output for LCD panel common plate
3/4
Note 2
Pull-high or 4-bit port for input only None. Note 3 Pull-high or 4-bit port for input only None. Note 3 3/4 3/4 Negative power supply, GND OSCI,OSCO are connected to an external resistor for an internal system clock
CMOS or NMOS Open 4-bit latch port for output only drain Pull-high or 4-bit port for input only None. Note 3 3/4 3/4 External interrupt input with pull high resistor Active on edge-triggered high to low transition Input to reset an internal LSI Reset is active on logical low level
27~30 31 32
PP0~PP3 INT RES
I I I
33 34~65 66
TMCLK SEG0~SEG31 VDD
I O I
Input for TIMER clock Pull-high or TIMER can be clocked by an external clock or an None. Note 4 internal frequency source. 3/4 3/4 LCD driver outputs for LCD panel segment Positive power supply
*Notes: 1. The system clock provides six different sources selectable by mask option to drive the sound effect clock. If the Holtek sound library is used, only 128K and 64K are acceptable. 2. Either (1/4 duty;1/3 bias) or (1/3 duty:1/3 bias) should be specified by mask option. 3. Each bit of ports PM, PS and PP can be a trigger source of the HALT interrupt, selectable by mask option. 4. 13 internal clock sources can be selectable by mask option to drive TMCLK. Note that TMCLK should not be connected to a pull high resistor if an internal source is used.
5
May 24, 1999
HT1130
Absolute Maximum Ratings
Supply Voltage ............................VDD-0.3V to 5.5V Storage Temperature.................-50C to 125C Input Voltage.................VSS-0.3V to VDD+0.3V Operating Temperature ..................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 RPH Parameter Operating Voltage Operating Current Standby Current Input Low Voltage Input High Voltage Port A, BZ and BZ Output Sink Current Port A, BZ and BZ Output Source Current Segment Output Sink Current Segment Output Source Current Pull-high Resistance Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 No load, fSYS=500kHz No load, HALT mode 3/4 3/4 VDD=3V, VOL=0.3V VDD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V PS, PP, PM, INT, RES, TMCLK Min. Typ. 2.4 3/4 3/4 0 2.1 1.5 -0.6 30 -20 30 3/4 500 3/4 3/4 3/4 3.0 -1.0 55 -40 3/4
Ta=25C Max. Unit 3.3 3/4 1 0.9 3.0 3/4 3/4 3/4 3/4 300 V mA mA V V mA mA mA mA kW
6
May 24, 1999
HT1130
A.C. Characteristics
Symbol fSYS fLCD tCOM tCY fTIMER tRES tINT fSOUND Notes: *: In general, fLCD is selected and optimized by Holtek depending upon fSYS and the operating voltage. **: Only these two clocking signal frequencies are supported by Holtek s sound library. Parameter System Clock LCD Clock LCD Common Period Cycle Time Timer I/P Frequency (TMCLK) Reset Pulse Width Interrupt Pulse Width Sound Effect Clock Test Conditions VDD 3V 3V 3/4 3/4 3V 3/4 3/4 3/4 Conditions R:620kW~36kW 3/4 1/3 duty 1/4 duty fSYS=1.0MHz 3/4 3/4 3/4 3/4 Min. 32 3/4 3/4 3/4 3/4 0 5 1 3/4 Typ. 3/4 256* (1/fLCD)3 (1/fLCD)4 4.0 3/4 3/4 3/4 64 or 128 ** Max. 1000 3/4 3/4 3/4 3/4 1000 3/4 3/4 3/4 Ta=25C Unit kHz Hz s s ms kHz ms ms kHz
7
May 24, 1999
HT1130
Functional Description
Program counter - PC This counter addresses the program ROM and is arranged as a 12-bit binary counter from PC0 to PC11 of which contents specify a maximum of 4096 addresses. The program counter counts with an increment of 1 or 2 with each execution of an instruction. When executing the jump instruction (JMP, JNZ, JC, JTMR,...), a subroutine call, initial reset, internal interrupt, external interrupt or returning from a subroutine, the program counter is loaded with the corresponding instruction data as shown in the table. Note: P0~P11: Instruction code @: PC11 keeps the current value S0~S11: Stack register bits Program memory - ROM The program memory is the executable memory and is arranged in a 40968 bit format. The address is specified by the program counter (PC). Four special locations are reserved and described as follows:
* Location 0
000H 004H 008H 00BH P ro g ra m Page N F00H FFFH P a g e F lo o k - u p ta b le ( 2 5 6 b y te s ) 8 b its lo o k - u p ta b le ROM R e s e t in itia l p r o g r a m T im e r in te r r u p t s u b r o u tin e E x te r n a l in te r r u p t s u b r o u tin e
Program memory
* Location 8
Activating the INT input pin of the processor with the interrupts enabled causes the program to jump to this location. Activating the PS, PP or PM input pins of the processor with the interrupts enabled during Halt mode also causes the program to jump to this location.
* Locations n00H to nFFH
Activating the processor RES pin causes the first instruction to be fetched from location 0.
* Location 4
Contains the timer interrupt resulting from a TIMER overflow. If the interrupts are enabled it causes the program to jump to this subroutine.
These are the 256 bytes of each page in the program memory. This area from n00H to nFFH and F00H to FFFH can be used as a look up table. Instructions such as READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or to ACC and a data memory address specified by the register pair R1,R0. However as R1,R0 can only store 8 bits, these instructions cannot fully specify the full 12 bit Program Counter
Mode Initial reset Internal interrupt External interrupt Jump, call instruction Conditional branch
PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 P11 @ 0 0 0 P10 P10 0 0 0 P9 P9 0 0 0 P8 P8 0 0 0 P7 P7 0 0 0 P6 P6 0 0 0 P5 P5 0 0 0 P4 P4 0 0 1 P3 P3 0 1 0 P2 P2 0 0 0 P1 P1 0 0 0 P0 P0
Program memory
8
May 24, 1999
HT1130
program memory address. For this reason a jump instruction should first be used to place the program counter in the right page. The above instructions can then be used to read the look up table data. Note that the page number n must be greater than zero as some locations in page 0 are reserved for specific usage. This area may function as a normal program memory when required. The program memory mapping is shown in the diagram. In the execution of an instruction the program counter is added before the execution phase, so careful manipulation of READ MR0A and READ R4A is needed in the page margin. Stack register The stack register is a group of registers used to save the contents of the program counter (PC) and is arranged in 13 bits 1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or an interrupt (indicated by a return instruction RET or RETI), the contents of the stack register are returned to the PC. Executing "RETI" instruction will restore the carry flag from the stack register, but RET does not. Working registers - R0, R1, R2, R3, R4 There are five working registers (R0, R1, R2, R3, R4) used to store the frequently accessed intermediate results. Using the instructions INC Rn and DEC Rn, the working registers can increment (+1) or decrement (-1). The JNZ Rn (n=0,1,4) instruction makes efficient use of the working registers as a program loop counter. The register pairs R0,R1 and R2,R3 are also used as a data memory pointer when the memory transfer instruction is executed. Data memory - RAM The static data memory (RAM) is arranged in 2564 bit format and is used to store data. All of the data memory locations are indirectly addressable through the register pair R1,R0 or R3,R2; for example MOV A,[R3R2] or MOV [R3R2],A. There are two areas in the data memory, the temporary data area and the display data area. Access to the temporary data area is from 00H to 7FH. Locations E0H to FFH represent the display data area. The locations between the temporary and display data areas are undefined and cannot be used. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals.
00H T e m p o ra ry D a ta A re a (1 2 8 x 4 ) U n d e fin e d A r e a (9 6 x 4 ) D is p la y D a ta A r e a (3 2 x 4 ) 4 b its D a ta R A M
80H
E0H FFH
Data memory
Accumulator - ACC The accumulator is the most important data register in the processor. It is one of the sources of input to the ALU and the destination of the results of the operations performed in the ALU. Data to and from the I/O ports and memory also pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs the following arithmetic and logic operations ...
* Add with or without carry * Subtract with or without carry * AND, OR, Exclusive-OR * Rotate right, left through carry
9
May 24, 1999
HT1130
* BCD decimal adjust for addition * Increment, decrement * Data transfers * Branch decisions
TIMER Frequency clock =
system clock 2n
where n=0, 1, 2 ...13 selectable by mask option Note that n cannot have the value of 6, which is reserved for internal use. Interrupt The HT1130 provides both internal and external interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. When the INT pin is triggered on a high to low transition in the enable interrupt mode and the program is not within a CALL subroutine, the external interrupt is activated. This causes a subroutine call to location 8 and resets the interrupt latch. Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine the internal interrupt is activated. This causes a subroutine call to location 4 and resets the timer flag. If both external and internal interrupts arrive at the same time then the external interrupt will be serviced first. When running under a CALL subroutine or DI the interrupt acknowledge is on hold until the RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable result may occur. If within a CALL subroutine both internal and external interrupts occur, no matter what order they arrive in, the external interrupt will be serviced first after leaving the CALL subroutine. This also applies if the two interrupts arrive at the same time. The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed. Each input port bit can be programmed by mask option to have an external interrupt function in the HALT mode.
The ALU not only outputs the results of data operations, but also sets the status of the carry flag (CF) in some instructions. Timer/counter The HT1130 contains a programmable 8-bit count-up counter which can be used to count external events or as a clock to generate an accurate time base. If the 8-bit timer clock is supplied by an external source from pin TMCLK then synchronization problems may occur when reading the data from the timer. It is therefore suggested that the timer is stopped before retrieving the data. The 8-bit counter will increment on the rising edge of the clock whether internally or externally generated. The timer/counter may be set and read with software instructions and stopped by a hardware reset or a TIMER OFF instruction. To restart the timer, load the counter with the value XXH and then issue a TIMER ON instruction. Note that XX is the desired start count immediate value for 8 bits. Once the timer/counter is started, it increments to a maximum count of FFH and then overflows to zero (00H). It then continues to count until stopped by a TIMER OFF instruction or a reset. The increment from the maximum count of FFH to a zero (00H) triggers a timer flag TF and an internal interrupt request. The interrupt may be enabled or disabled by executing the EI and DI instruction. If the interrupt is enabled, the timer overflow will cause a subroutine call to location 4. The state of the timer flag is also testable with the conditional jump instruction JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed. If an internal source is used, the frequency is determined by the system clock and the parameter n as defined in the equation. The frequency of the internal frequency source can be selected by mask option.
10
May 24, 1999
HT1130
Initial reset The HT1130 provides an RES pin for system initialization. This pin is equipped with an internal pull high resistor and in combination with an external 0.1m~1mF capacitor, provides an internal reset pulse of sufficient length to guarantee a reset to all internal circuits. If the reset pulse is generated externally, the RES pin must be held low for at least 5ms. Normal circuit operation will not commence until the RES pin returns high. The reset performs the following functions:
* Sets the program counter PC to 000H * Disables the interrupt mode * Stops the timer * Resets the timer and timer flag * Clears the carry flag * Sets the sound off and one sing mode * Sets port A high or floating
Case 1: If the system is in an interrupt-disable state before entering the halt state:
* The instruction HALT is executed and the
system enters a halt state
* A falling edge transition on INT, or on any of
the wake up pins on ports PP, PS or PM, will awaken the system and return to the main program instruction following the HALT command.
* An interrupt signal, whether caused by INT
or the ports PP,PS or PM, will be held until the system receives an enable interrupt command at which point the held interrupt will be serviced. Case 2: If the system is in an interrupt enable state:
* The instruction HALT is executed and the
system enters a halt state
* A falling edge transition on INT, or on any of
Halt This is a special feature of the HT1130 to interrupt the chip s normal operation and reduce power consumption. When a HALT is executed the following happens ...
* The system clock will be stopped. * The contents of the on-chip RAM and regis-
the wake up pins on ports PP, PS or PM, will awaken the system and execute the external interrupt subroutine Sound effects The HT1130 includes sound effect circuitry which offers up to 16 sounds with 3 tones, boom and noise effects. Holtek supports a sound library which has melodies, alarms, machine guns etc.. Whenever the instruction "SOUND n" or "SOUND A" is executed, the specified sound will begin. Whenever "SOUND OFF" is executed, it terminates the singing sound immediately. There are two singing modes, SONE mode and SLOOP mode activated by SOUND ONE and SOUND LOOP. In SONE mode the specified sound plays just once. In SLOOP mode the specified sound keeps re-playing. Since sounds 0~11 contain 32 notes and sounds 12~15 contain 64 notes the latter possesses better sound than the former. The frequency of the sound effect circuit can be selected by mask option.
ters remain unchanged.
* All of the LCD segments and commons will
have the VLCD voltage so the LCD becomes blank. The halt status can be terminated by an external interrupt or a hardware reset. In the HALT mode any bit of ports PP, PS, PM can be used as external interrupts set by mask option to wake-up the system. This signal is active on a low-going transition. When the halt status is terminated by an external interrupt, the following procedure takes place ...
11
May 24, 1999
HT1130
Frequency of sound effect circuit = where m=0, 1, 2, 3, 4, 5
1 256Hz VL VL VL VL VL VL VL VL VL VL VL VL VL VL VL VL VL VL VL VL CD C1 C2 C3 CD C1 C2 C3 CD C1 C2 C3 CD C1 C2 C3 CD C1 C2 C3
system clock 2m
64Hz 2 3 4 1 2 3 4 1 2 3 4
Holtek s sound library supports only sound clock frequencies of 128K or 64K. To use Holtek s sound library, the proper system clock and mask option should be selected. LCD display memory As mentioned in the data memory section the LCD display memory is embedded in the data memory. It can be read and written to in the same way as normal data memory. The figures show the mapping between the display memory and LCD pattern for the HT1130. To turn the display on or off an 1/0 is written to the corresponding bit of the display memory. The LCD display module may have any form as long as the number of commons does not exceed 4 and the number of segments does not exceed 32.
COM0
COM1
COM2
COM3
SEG0
LCD driver output LCD driver output All LCD segments are random after an initial clear. The bias voltage circuits of the LCD display is built-in and no external resistor is needed. The output number of the HT1130 LCD driver is 324 which can directly drive an LCD with 1/4 (or 1/3 by mask option) duty cycle and 1/3 bias.
COM 0 1 2 3
FFH
D IS P L A Y M E M O R Y FEH FDH FCH E2H
E1H
E0H
B IT 0 1 2 3
The frequency of the LCD driving clock is fixed at about 256Hz. This is set by Holtek according to the application and cannot be changed.
SEGMENT
31
30
29
28
2
1
0
LCD display memory
12
May 24, 1999
HT1130
Oscillator Only one external resistor is needed for the HT1130 oscillator circuit. The system clock is also used as the reference signal of the LCD driving clock, sound effect clock and internal frequency source of the TIMER. One HT1130 machine cycle consists of a sequence of four states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4.0ms if the system frequency is up to 1.0MHz. Output port - PA A mask option is available to select whether the output is a CMOS or open drain NMOS type. After an initial clear the output port PA defaults to be high for CMOS or floating for NMOS.
VDD
in te r n a l b u s
OSCI
D CK Q
Q
m a s k o p tio n
R
HT1130
OSCO
RC oscillator Interfacing The HT1130 microcontroller communicate with the outside world through three 4-bit input ports PP, PS and PM and one 4-bit output port PA. Input ports - PP, PS, PM All ports can have internal pull high resistors determined by mask option. Every bit of the input ports PP, PS and PM can be specified to be a trigger source to wake up the HALT interrupt by mask option. A high to low transition on one of these pins will wake up the device from a HALT status. Mask options
Output port - PA
The following options are available by mask option which must be selected prior to manufacturing.
* 4-bit input ports PP, PS and PM with or with-
out pull high resistors.
* Each bit of PP, PS and PM can wake up the
processor from a HALT state.
* Output Port PA as CMOS or open drain NMOS. * 8-bit programmable timer with external clock
VDD
w a k e -u p p u ll- h ig h m ask o p tio n w a k e -u p m ask o p tio n re a d c o n tro l
or internal frequency source. Thirteen internal frequency sources are available to provide an internal clock. Note that a value of n=6 cannot be used for the devices. If the internal frequency sources are used as a clocking signal then TMCLK cannot be connected to a pull-high resistor
* Six kinds of sound clock frequency:
fSYS/2 , m=0, 1, 2, 3, 4, 5
in te r n a l b u s
m
Input ports - PP, PS, PM
* Two kinds of LCD applications: 1/4 duty 1/3
bias or 1/3 duty 1/3 bias
13
May 24, 1999
HT1130
Software Tools To make the programming task easier and to reduce development time Holtek supplies a development system for the HT1130. The system runs under an IBM PC-XT/AT environment and consists of both a hardware emulation board and a suite of programs including powerful debug functions. The user can download the code from the PC to the emulation board for verification. The main features of the system are as follows.
* Can incorporate the user s text editor or word * Provides symbolic debugging capabilities * User defined mask options * RC with variable resistor * Displays and modifies registers, carry flag,
timer, port output level and internal RAM
* Single instruction stepping * Jumps unconditionally to any address and
halts anytime during execution
* Provides up to 8 breakpoint settings * Real time 255 forward step or 256 backward
processor with Holtek s cross assembler to form an integrated development system
* Supports mouse functions with its window
step trace After program verification on the emulation board the customer supplies Holtek with the verified code prior to manufacturing.
based human interface
* Performs stand-alone operation for demon-
stration purposes
* Auto-executes self test function at every
power on reset
14
May 24, 1999
HT1130
Application Circuits
PA0 PA1 PA2 PA3 PM0 PM1 PM2 PM3 OUTPUT PORT CO CO CO CO M0 M1 M2 M3 X32
IN P U T PORT
L Pa (1 /3 1 /4
CD tte rn B ia s , D u ty )
SEGMENT OUTPUT
PS0 PS1 PS2 PS3 R*
IN P U T PORT
BZ
P ie z o B uzzer
BZ
HT1130
OSCI OSCO
PP0 PP1 PP2 PP3
IN P U T PORT
VLC D
L C D P o w e r s u p p ly
**
IN T TM C LK
RES
0 . 1 F ~ 1 F
Notes:
R*: Depends on the required system clock frequency (R=36kW~620kW, at VDD=3V). **: Timer clock may come from an external or internal frequency source.
15
May 24, 1999
HT1130
Instruction Set Summary
Mnemonic Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment and Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH Move register to ACC, n=0~4 Move ACC to register, n=0~4 Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Increment ACC Increment register, n=0~4 Increment data memory Increment data memory Decrement ACC Decrement register, n=0~4 Decrement data memory Decrement data memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition 1 1 1 1 2 2 1 1 1 1 1 2 2 1
O O O O O O O
Description
Byte
Cycle
CF
16
May 24, 1999
HT1130
Mnemonic Rotate RL A RLC A RR A RRC A Input and Output IN A,Pi OUT PA,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Set 8 bits immediate data to TIMER Set TIMER start counting Set TIMER stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to hight nibble of TIMER 2 1 1 1 1 1 1 2 1 1 1 1 1 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation 1 1 1 1 1 1 1 1 1 1 0 1 3/4 3/4 3/4 Subroutine call Return from subroutine or interrupt Return from interrupt service routine 2 1 1 2 1 1 3/4 3/4 O Jump unconditionally Jump on carry=1 Jump on carry=0 Jump on timer overflow Jump on ACC bit n=1 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Input port-i to ACC, port-i=PM, PS, PP Output ACC to port-A 1 1 1 1 3/4 3/4 Rotate ACC left Rotate ACC left through the carry Rotate ACC right Rotate ACC right through the carry 1 1 1 1 1 1 1 1
O O O O
Description
Byte
Cycle
CF
17
May 24, 1999
HT1130
Mnemonic Table Read READ R4A READ MR0A READF R4A READF MR0A Sound Control SOUND n SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT Enter power down mode 2 2 3/4 Activate SOUND channel n Activate SOUND channel with ACC Turn on SOUND one cycle Turn on SOUND repeat cycle Turn off SOUND 2 1 1 1 1 2 1 1 1 1 3/4 3/4 3/4 3/4 3/4 Read ROM code of current page to R4 and ACC Read ROM code of current page to M(R1,R0), ACC Read ROM code of page F to R4 and ACC Read ROM code of page F to M(R1,R0),ACC 1 1 1 1 2 2 2 2 3/4 3/4 3/4 3/4 Description Byte Cycle CF
18
May 24, 1999
HT1130
Instruction Definitions
ADC A,[R1R0] Machine code Description Operation ADD A,XH Machine code Description Operation ADD A,[R1R0] Machine code Description Operation AND A,XH Machine code Description Operation AND A,[R1R0] Machine code Description Add data memory contents and carry to the accumulator 00001000 The contents of the data memory addressed by the register pair "R1,R0" and the carry are added to the accumulator. Carry is affected. ACC ACC+M(R1,R0)+CF Add immediate data to the accumulator 01000000 0000dddd The specified data is added to the accumulator. Carry is affected. ACC ACC+XH Add data memory contents to the accumulator 00001001 The contents of the data memory addressed by the register pair "R1,R0" is added to the accumulator. Carry is affected. ACC ACC+M(R1,R0) Logical AND immediate data to accumulator 01000010 0000dddd Data in the accumulator is logical AND with the immediate data specified by the code. ACC ACC "AND" XH Logical AND accumulator with data memory 00011010 Data in the accumulator is logical AND with the data memory addressed by the register pair "R1,R0" Operation ACC ACC "AND" M(R1,R0) AND [R1R0],A Machine code Description Operation Logical AND data memory with accumulator 00011101 Data in the data memory addressed by the register pair "R1,R0" is logical AND with the accumulator M(R1,R0) M(R1,R0) "AND" ACC
19
May 24, 1999
HT1130
CALL address Machine code Description Operation Subroutine call 1111aaaa aaaaaaaa The program counter bits 0~11 are saved in the stack and the specified address loaded into the program counter. Stack PC+2 PC address Clear carry flag 00101010 The carry flag is reset to zero. CF 0 Decimal-Adjust accumulator 00110110 The accumulator value is adjusted to BCD (Binary Code Decimal), if the contents of the accumulator is greater than 9 or CF (Carry flag) is 1. If ACC>9 or CF=1 then ACC ACC+6, CF 1 else ACC ACC, CF CF Decrement accumulator 00111111 Data in the accumulator is decremented by 1. Carry flag is not affected. ACC ACC-1 Decrement register 0001nnn1 Data in the working register "Rn" is decremented by 1. Carry flag is not affected. Rn Rn-1; Rn=R0,R1,R2,R3, R4, for n=0, 1, 2, 3, 4 Decrement data memory 00001101 Data in the data memory specified by the register pair "R1,R0" is decremented by 1. Carry flag is not affected. M(R1,R0) M(R1,R0) 1
CLC Machine code Description Operation DAA Machine code Description Operation
DEC A Machine code Description Operation DEC Rn Machine code Description Operation DEC [R1R0] Machine code Description Operation
20
May 24, 1999
HT1130
DEC [R3R2] Machine code Description Operation DI Machine code Description EI Machine code Description HALT Machine code Description Operation IN A,Pi Machine code Decrement data memory 00001111 Data in the data memory specified by the register pair "R3,R2" is decremented by 1. Carry flag is not affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00101101 Internal time-out interrupt and external interrupt are disabled. Enable interrupt 00101100 Internal time-out interrupt and external interrupt are enabled. Halt system clock 00110111 PC PC+2 Input port to accumulator PM PS PP Description Operation INC A Machine code Description Operation INC Rn Machine code Description Operation 00110010 00110011 00110100 00111110 Turn off system clock, and enter power down mode.
The data on port "Pi" is transferred to the accumulator. ACC Pi; Pi=PM, PS or PP Increment accumulator 00110001 Data in the accumulator is incremented by 1. Carry flag is not affected. ACC ACC+1 Increment register 0001nnn0 Data in the working register "Rn" is incremented by 1. Carry flag is not affected. Rn Rn+1; Rn=R0~R4 for n=0~4
21
May 24, 1999
HT1130
INC [R1R0] Machine code Description Operation INC [R3R2] Machine code Description Operation JAn address Machine code Description Increment data memory 00001100 Data in the data memory specified by the register pair "R1,R0" is incremented by 1. Carry flag is not affected. M(R1,R0) M(R1,R0)+1 Increment data memory 00001110 Data memory specified by the register pair "R3,R2" is incremented by 1. Carry flag is not affected. M(R3,R2) M(R3,R2)+1 Jump if accumulator bit n is set 100nnaaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if accumulator bit n is set to 1. PC (bit 0~10) address, if ACC bit n=1(n=0~3) PC PC+2, if ACC bit n=0 Jump if carry is set 11000aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the CF (Carry flag) is set to 1. PC (bit 0~10) address, if CF=1 PC PC+2, if CF=0 Direct jump 1110aaaa aaaaaaaa Bits 0~11 of the program counter are replaced with the directly-specified address. PC address Jump if carry is not set 11001aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address and bit 11 of the program counter is unaffected, if the CF (Carry flag) is set to 0. PC (bit 0~10) address, if CF=0 PC PC+2, if CF=1
Operation
JC address Machine code Description
Operation
JMP address Machine code Description Operation JNC address Machine code Description
Operation
22
May 24, 1999
HT1130
JNZ A,address Machine code Description Jump if accumulator is not 0 10111aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the accumulator is not 0. PC (bit 0~10) address, if ACC0 PC PC+2, if ACC=0 Jump if register is not 0 R0 R1 R4 Description 10100aaa 10101aaa 11011aaa aaaaaaaa aaaaaaaa aaaaaaaa
Operation
JNZ Rn,address Machine code
Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the register is not 0. PC (bit 0~10) address, if Rn0; Rn=R0 ,R1, R4 PC PC+2, if Rn=0 Jump if time-out 11010aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the TF (Timer flag) is set to 1. PC (bit 0~10) address, if TF=1 PC PC+2, if TF=0 Jump if accumulator is 0 10110aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the accumulator is 0. PC (bit 0~10) address, if ACC=0 PC PC+2, if ACC0 Move register to accumulator 0010nnn1 Data in the working register "Rn" is moved to the accumulator. ACC Rn; Rn=R0~R4, for n=0~4
Operation
JTMR address Machine code Description
Operation
JZ A,address Machine code Description
Operation
MOV A,Rn Machine code Description Operation
23
May 24, 1999
HT1130
MOV A,TMRH Machine code Description Operation MOV A,TMRL Machine code Description Operation MOV A,XH Machine code Description Operation MOV A,[R1R0] Machine code Description Operation MOV A,[R3R2] Machine code Description Operation MOV R1R0,XXH Machine code Description Move timer high nibble to accumulator 00111011 The high nibble data of the timer counter is loaded to the accumulator. ACC TIMER (high nibble) Move timer low nibble to accumulator 00111010 The low nibble data of the timer counter is loaded to the accumulator. ACC TIMER (low nibble) Move immediate data to accumulator 0111dddd The 4-bit data specified by the code is loaded to the accumulator. ACC XH Move data memory to accumulator 00000100 Data in the data memory specified by the register pair "R1,R0" is moved to the accumulator. ACC M(R1,R0) Move data memory to accumulator 00000110 Data in the data memory specified by the register pair "R3,R2" is moved to the accumulator. ACC M(R3,R2) Move immediate data to R1 and R0 0101dddd 0000dddd The 8-bit data specified by the code is loaded to the working registers R1 and R0, the high nibble of the data is loaded to R1, and the low nibble to R0. R1 XH (high nibble) R0 XH (low nibble) Move immediate data to R3 and R2 0110dddd 0000dddd The 8-bit data specified by the code is loaded to the working registers R3 and R2, the high nibble of the data is loaded to R3, and the low nibble to R2. R3 XH (high nibble) R2 XH (low nibble)
Operation
MOV R3R2,XXH Machine code Description
Operation
24
May 24, 1999
HT1130
MOV R4,XH Machine code Description Operation MOV Rn,A Machine code Description Operation MOV TMRH,A Machine code Description Operation MOV TMRL,A Machine code Description Operation MOV [R1R0],A Machine code Description Operation MOV [R3R2],A Machine code Description Operation NOP Machine code Description Move immediate data to R4 01000110 R4 XH Move accumulator to register 0010nnn0 Data in the accumulator is moved to the working register "Rn". Rn ACC; Rn=R0~R4, for n=0~4 Move accumulator to timer high nibble 00111101 The contents of the accumulator is loaded to the high nibble of the timer counter. TIMER(high nibble) ACC Move accumulator to timer low nibble 00111100 The contents of the accumulator is loaded to the low nibble of the timer counter. TIMER(low nibble) ACC Move accumulator to data memory 00000101 Data in the accumulator is moved to the data memory specified by the register pair "R1,R0". M(R1,R0) ACC Move accumulator to data memory 00000111 Data in the accumulator is moved to the data memory specified by the register pair "R3,R2". M(R3,R2) ACC No operation 00111110 Do nothing, but one instruction cycle is delayed. 0000dddd The 4-bit data specified by the code is loaded to the working register R4.
25
May 24, 1999
HT1130
OR A,XH Machine code Description Operation OR A,[R1R0] Machine code Description Operation OR [R1R0],A Machine code Description Operation OUT PA,A Machine code Description Operation READ MR0A Machine code Description Logical OR immediate data to accumulator 01000100 0000dddd Data in the accumulator is logical OR with the immediate data specified by the code. ACC ACC "OR" XH Logical OR accumulator with data memory 00011100 Data in the accumulator is logical OR with the data memory addressed by the register pair "R1,R0". ACC ACC "OR" M(R1,R0) Logically OR data memory with accumulator 00011111 Data in the data memory addressed by the register pair "R1,R0" is logical OR with the accumulator. M(R1,R0) M(R1,R0) "OR" ACC Output accumulator data to port A 00110000 The data in the accumulator is transferred to port PA and latched. PA ACC Read ROM code of current page to M(R1,R0) and ACC 01001110 The 8-bit ROM code (current page) addressed by ACC and R4 is moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code is specified as below: Current page (R) ROM code address bit 11~8 ACC (R) ROM code address bit 7~4 R4 (R) ROM code address bit 3~0 M(R1,R0) ROM code (high nibble) ACC ROM code (low nibble)
Operation
26
May 24, 1999
HT1130
READ R4A Machine code Description Read ROM code of current page to R4 and accumulator 01001100 The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) is moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code is specified as below: Current page (R) ROM code address bit 11~8 ACC (R) ROM code address bit 7~4 M(R1,R0) (R) ROM code address bit 3~0 R4 ROM code (high nibble) ACC ROM code (low nibble) Read ROM Code of page F to M(R1,R0) and ACC 01001111 The 8-bit ROM code (page F) addressed by ACC and R4 is moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. Page F (R) ROM code address bit 11~8 are "1111" ACC (R) ROM code address bit 7~4 R4 (R) ROM code address bit 3~0 M(R1,R0) high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Read ROM code of page F to R4 and accumulator 01001101 The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) is moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. Page F (R) ROM code address bit 11~8 are "1111" ACC (R) ROM code address bit 7~4 M(R1,R0) (R) ROM code address bit 3~0 R4 high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Return from subroutine or interrupt 00101110 The program counter bits 0~11 are restored from the stack. PC Stack
Operation
READF MR0A Machine code Description
Operation
READF R4A Machine code Description
Operation
RET Machine code Description Operation
27
May 24, 1999
HT1130
RETI Machine code Description Operation Return from interrupt subroutine 00101111 The program counter bits 0~11 are restored from the stack. The carry flag before entering the interrupt service routine is restored. PC Stack CF CF (before interrupt service routine) Rotate accumulator left 00000001 The contents of the accumulator are rotated left 1 bit. Bit 3 is rotated to both bit 0 and the carry flag. An+1 An, An: accumulator bit n (n=0, 1, 2) A0 A3 CF A3 Rotate accumulator left through carry 00000011 The contents of the accumulator are rotated left 1 bit. Bit 3 replaces the carry bit, which is rotated into the bit 0 position. An+1 An, An: Accumulator bit n (n=0, 1, 2) A0 CF CF A3 Rotate accumulator right 00000000 The contents of the accumulator are rotated right 1 bit. Bit 0 is rotated to both bit 3 and the carry flag. An An+1, An: Accumulator bit n (n=0, 1, 2) A3 A0 CF A0 Rotate accumulator right through carry 00000010 The contents of the accumulator are rotated right 1 bit. Bit 0 replaces the carry bit, which bit is rotated into the bit 3 position. An An+1, An: Accumulator bit n (n=0,1,2) A3 CF CF A0
RL A Machine code Description Operation
RLC A Machine code Description Operation
RR A Machine code Description Operation
RRC A Machine code Description Operation
28
May 24, 1999
HT1130
SBC A,[R1R0] Machine code Description Subtract data memory contents and carry from ACC 00001010 The contents of the data memory addressed by the register pair "R1,R0" and the complement of the carry are subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+M(R1,R0)+CF Activate SOUND channel with accumulator 01001011 The activated sound begins playing in accordance with the contents of the accumulator when the specified sound channel is matched. Turn on sound repeat cycle 01001001 The activated sound plays repeatedly. Turn off sound 01001010 The activated sound will terminate immediately. Turn on sound 1 cycle 01001000 The activated sound plays once. Activate SOUND channel n 01000101 0000nnnn The specified sound begins playing and overwrites the previous activated sound (n=0~15). Set carry flag 00101011 The carry flag is set to 1. CF 1 Subtract immediate data from accumulator 01000001 0000dddd The specified data is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+XH+1
Operation SOUND A Machine code Description
SOUND LOOP Machine code Description SOUND OFF Machine code Description SOUND ONE Machine code Description SOUND n Machine code Description
STC Machine code Description Operation SUB A,XH Machine code Description Operation
29
May 24, 1999
HT1130
SUB A,[R1R0] Machine code Description Subtract data memory contents from accumulator 00001011 The contents of the data memory addressed by the register pair "R1,R0" is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+M(R1,R0)+1 Set timer to stop counting 00111001 The timer stops counting, when the "TIMER OFF" instruction is executed. Set timer to start counting 00111000 The timer starts counting, when the "TIMER" ON instruction is executed. Set immediate data to timer counter 01000111 TIMER XXH Logical XOR immediate data to accumulator 01000011 0000dddd Data in the accumulator is Exclusive-OR with the immediate data specified by the code. ACC ACC "XOR" XH Logical XOR accumulator with data memory 00011011 Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair "R1,R0". ACC ACC "XOR" M(R1,R0) Logical XOR data memory with accumulator 00011110 Data in the data memory addressed by the register pair "R1,R0" is logically Exclusive-OR with the accumulator. M(R1,R0) M(R1,R0) "XOR" ACC dddddddd The 8-bit data specified by the code is loaded to the timer counter.
Operation TIMER OFF Machine code Description
TIMER ON Machine code Description
TIMER XXH Machine code Description Operation XOR A,XH Machine code Description Operation XOR A,[R1R0] Machine code Description Operation XOR [R1R0],A Machine code Description Operation
30
May 24, 1999
HT1130
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright 1999 by HOL TEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
31
May 24, 1999

▲Up To Search▲

Price & Availability of HT1130

	To Download HT1130 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .